The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. Advantages of the FinFET may include reducing the short channel effect and higher current flow.
Although existing FinFETs and methods of fabricating FinFETs have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, as the size of the fin (e.g., the fin width) and the fin-to-fin space (i.e., the distance between two adjacent fins) are reduced, the resistance of the well pick-up region is increased due to the interdiffusion between the well pick-up regions with different conductivity types, and thus the electrical performance of the semiconductor device is reduced. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.